Staff Lead Design Verification Engineer (OX1050)

Today’s dynamic global security threats require solutions both big and small – solutions living within the Northrop Grumman Microelectronics Center (NGMC). Boasting state-of-the-art design capabilities, multiple processing nodes, electrical testing, environmental and QCI screening, and failure analysis, the NGMC is a leader in designing, fabricating, packaging and delivering discriminating microelectronics to the military, aerospace, and commercial markets.  For more than 70 years, we have been offering a wide range of trusted foundry and semiconductor services that deliver high performing and reliable microelectronics. Our wide breadth of technologies and capabilities allows us to provide our customers with unique “More than Moore” solutions.

What You'll Get To Do:

As a Digital Verification Lead Engineer, you will have an opportunity to be a part of a technology development organization that is collaborative, open, transparent, team-oriented, and flexible, where continuous learning is encouraged, all within a culture of design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal candidate will play a critical role in behavioral simulation, and comprehensive functional verification processes.

Role and Responsibilities:

The Debug and Staff Lead Design Verification Engineer will be responsible leading the verification team for debug, emulation, and test development for state-of-the-art Digital Logic (High Speed Serial). Other responsibilities will include:

Design Entry and RTL Development:

• Create comprehensive test-benches for behavioral simulation

• Design and implement verification strategies for complex digital systems

• Ensure RTL implementation meets precise design specification requirements

Functional Verification:

• Conduct in-depth behavioral simulations across ASIC and FPGA

• Generate and execute advanced UVM Test cases

• Achieve 95% code coverage goals and functional coverage across critical metrics

• Perform detailed code coverage analysis, including: (Statement coverage, Expression coverage, Branch coverage, Toggle coverage)

Simulation:

• Utilize both functional and timing simulation tools

• Verify logical behavior and implementation accuracy

• Identify and resolve signal delay and performance issues in gate timing requirements

• Develop comprehensive Universal Verification Methodology (UVM) simulation environments

Collaborative Processes:

• Work closely with design teams to validate RTL implementations

• Provide detailed feedback and recommendations for design improvements

• Participate in design reviews and Lead in verification planning

• Mentor junior verification engineers

• Contribute to continuous improvement of verification methodologies

This position is contingent upon clearance.

This position will serve on-site in Linthicum/ Annapolis Junction, MD.

Basic Qualifications for Staff Lead Design Verification Engineer:

• Bachelor's degree in Computer Engineering, BSEE, or comparable STEM Degree and 12 years industry experience in a design verification role or Master’s Degree plus 10 years experience or PhD plus 8 years experience

• Experience with functional verification methodology for the full life cycle of products with leading a team with various levels of experience and skills

• Demonstrated experience leading Verification Teams

• Specialized experience in functional verification with multiple Tape Outs

• Expert-level proficiency in Hardware Description Languages: (Verilog, VHDL, SystemVerilog)

• Extensive knowledge of: (comprehensive RTL design methodologies, Behavioral simulation techniques, Code coverage strategies)

• Extensive experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics)

• Extensive experience with verification methodologies: Universal Verification Methodology (UVM)

• Regression and automation framework development

• This position requires the applicant to be a U.S. citizen

• Current active DoD TS/SCI with poly clearance per business requirements.

Preferred Qualifications for Staff Lead Design Verification Engineer:

• Advanced Degrees in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields

• Experience with advanced Gate Level Simulations

• Experience with the management of schedule, cost, metric reporting, and trade studies

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Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.